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TECHNICAL DATA
IN74AC109
Dual J-K Flip-Flop with Set and Reset
High-Speed Silicon-Gate CMOS
The IN74AC109 is identical in pinout to the LS/ALS109,HC/HCT109. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LS/ALS outputs. This device consists of two J-K flip-flops with individual set, reset, and clock inputs. Changes at the inputs are reflected at the outputs with the next low-to-high transition of the clock. Both Q to Q outputs are available from each flip-flop. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A; 0.1 A @ 25C * High Noise Immunity Characteristic of CMOS Devices * Outputs Source/Sink 24 mA
ORDERING INFORMATION IN74AC109N Plastic IN74AC109D SOIC TA = -40 to 85 C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs Set L H L H H H H PIN 16=VCC PIN 8 = GND Reset H L L H H H H Clock X X X J X X X L H L H K X X X L L H H H Outputs Q H L H
*
Q L H H* H Toggle
L
No Change L
H H L XX No Change X = Don't care * Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
117
IN74AC109
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 20 50 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TJ TA IOH IOL tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Junction Temperature (PDIP) Operating Temperature, All Package Types Output Current - High Output Current - Low Input Rise and Fall Time (except Schmitt Inputs)
*
Min 2.0 0 -40
Max 6.0 VCC 140 +85 -24 24
Unit V V C C mA mA ns/V
VCC =3.0 V VCC =4.5 V VCC =5.5 V
0 0 0
150 40 25
*
VIN from 30% to 70% VCC
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
118
IN74AC109
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol VIH Parameter Minimum High-Level Input Voltage Maximum Low Level Input Voltage Minimum High-Level Output Voltage Test Conditions VOUT=0.1 V or VCC-0.1 V V 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 5.5 5.5 5.5 5.5 4.0 Guaranteed Limit 25 C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 -40C to 85C 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 1.0 75 -75 40 A mA mA A V Unit V
VIL
VOUT=0.1 V or VCC-0.1 V
V
VOH
IOUT -50 A
V
*
VIN=VIH or VIL IOH=-12 mA IOH=-24 mA IOH=-24 mA VOL Maximum Low-Level Output Voltage IOUT 50 A
VIN=VIH or VIL IOL=12 mA IOL=24 mA IOL=24 mA IIN IOLD IOHD ICC Maximum Input Leakage Current +Minimum Dynamic Output Current +Minimum Dynamic Output Current Maximum Quiescent Supply Current (per Package) VIN=VCC or GND VOLD=1.65 V Max VOHD=3.85 V Min VIN=VCC or GND
*
All outputs loaded; thresholds on input associated with output under test. +Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V VCC
*
119
IN74AC109
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=3.0 ns)
VCC* Symbol Parameter V Guaranteed Limits 25 C Min fmax tPLH tPHL tPLH tPHL CIN Maximum Clock Frequency (Figure 1) Propagation Delay , Clock to Q or Q (Figure 1) Propagation Delay , Clock to Q or Q (Figure 1) Propagation Delay , Set or Reset to Q or Q (Figure 2) Propagation Delay , Set or Reset to Q or Q (Figure 2) Maximum Input Capacitance 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 5.0 125 150 4.0 2.5 3.0 2.0 3.0 2.5 3.0 2.0 4.5 13.5 10.0 14.0 10.0 12.0 9.0 12.0 9.5 Max -40C to 85C Min 100 125 3.5 2.0 3.0 1.5 2.5 2.0 3.0 2.0 4.5 16.0 10.5 14.5 10.5 13.0 10.0 13.5 10.5 Max MHz ns ns ns ns pF Unit
Typical @25C,VCC=5.0 V CPD
*
Power Dissipation Capacitance
35
pF
Voltage Range 3.3 V is 3.3 V 0.3 V Voltage Range 5.0 V is 5.0 V 0.5 V
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=3.0 ns)
VCC* Symbol tsu th tw trec
*
Guaranteed Limits 25 C 6.5 4.5 0 0.5 4.0 3.5 0 0 -40C to 85C 7.5 5.0 0 0.5 4.5 3.5 0 0 Unit ns ns ns ns
Parameter Minimum Setup Time, J or K to Clock (Figure 3) Minimum Hold Time, Clock to J or K (Figure 3) Minimum Pulse Width, Set, Reset, Clock (Figures 1,2) Minimum Recovery Time, Set or Reset to Clock (Figure 2)
V 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Voltage Range 3.3 V is 3.3 V 0.3 V Voltage Range 5.0 V is 5.0 V 0.5 V
120
IN74AC109
Figure 1. Switching Waveform
Figure 2. Switching Waveform
Figure 3. Switching Waveform
EXPANDED LOGIC DIAGRAM
121

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